1. The Field of the Invention
The present invention generally relates to formation of vias. More particularly, the present invention relates to the formation of semiconductor devices having vias that are more reliable and free of defects.
2. The Relevant Technology
Integrated circuits are manufactured by an elaborate process in which a variety of different microelectronic devices are integrally formed on a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) structure. In advanced manufacturing of integrated circuits, hundreds of thousands of electronic devices can be formed on a single substrate.
One of the steps in the fabrication of integrated circuits is to form generally horizontal metallic interconnection or wire lines between the discrete microelectronic devices on the integrated circuit and to external circuitry. The horizontal metallic interconnections are conducting layers that permit an electrical current to be delivered to and from the various microlectronic devices so that the integrated circuit can perform its intended function. Since the integrated circuitry needed for a semiconductor is usually build-up three-dimensionally on the substrate in order to increase the packing density and so forth, multi-level metallizations are generally necessary and employed in which inter-level dielectric layers are interposed between different metallization levels formed on the device substrate.
Vias, also referred to as xe2x80x9cvertical interconnects,xe2x80x9d are used to electrically connect different horizontal levels of metallization. The via is a via hole or through hole filled with a conductor material that extends through a dielectric interposed between surfaces of two separate horizontal metallization levels. The metallization process is repeated as needed to form additional levels and to form a plurality of similar horizontal and vertical conductive interconnections. Among other things, the yield, performance and reliability of the semiconductor device critically depend on the stability and integrity of the vias.
Referring to FIG. 5, a conventional via structure is shown in which a first horizontal metallic interconnection layer 51 is formed on a first dielectric layer 50 that has previously been formed on a substrate or an inter-level dielectric, depending on which two metallization levels are being interconnected. The first interconnection layer 51 commonly is aluminum or an aluminum alloy layer material, such as Al, Alxe2x80x94Cu or Alxe2x80x94Cuxe2x80x94Si. An anti-reflective coating (ARC) layer 52 is formed on the surface of the first interconnection layer 51. A second dielectric layer 53 is formed on the first interconnection layer 51 (and the ARC layer 52). A via-hole 500 is formed through dielectric layer 53 and the ARC layer 52 to expose a discrete surface region of the first interconnection layer 51 at the bottom of the via hole 500. The via hole 500 is lined with a titanium layer 54 and titanium nitride layer 55 (i.e., Ti/TiN) provided on the sidewalls and bottom of the via hole 500. Then, a refractory metal is deposited in the via hole 500 hole to form a conductive via plug 56. A conventional way to form the refractory metal plug 56 is by forming tungsten on the lined via hole 500 by hydrogen or silane reduction of tungsten hexafluoride (WF6) in a CVD process. Tungsten formed by chemical vapor deposition (CVD) has poor adhesion to commonly used inter-level dielectrics such as silicon oxides. The Ti layer 54 is a good dielectric-to-metal adhesion layer, forms a good ohmic contact, and reduces surface oxides on the aluminum. However, the Ti layer 54 tends to adversely react with refractory halide precursors commonly used in depositing the refractory metal plug 56, such as tungsten hexafluoride. TiN provides a protective barrier for the Ti to suppress such undesired reactions. Hence, the TiN overlayer 55 is used as an additional component of the conventional dual-layer via lining under discussion. After deposition of the refractory metal plug 56, the workpiece surface is planarized so that the surface of the plug 56 is made co-planar with the second dielectric layer 53. A second metallic interconnection layer, not shown, then would be formed on the planarized plug 56 and second dielectric layer 53.
However, when titanium is put in contact with aluminum, such as occurs at the interface between the Ti layer 54 and a surface portion of a first aluminum interconnection layer 51 exposed at the bottom of via hole 500, the titanium and aluminum tend to react during high temperature processing. This results in the formation of a titanium aluminide region at or near their interface. For instance, as indicated in FIG. 5, a titanium aluminide region 57 has formed in this manner at the bottom region of the via, such as during the deposition of tungsten by CVD as the refractory plug 56 or a subsequent post metal deposition anneal procedure. It is known that titanium aluminide, viz., TiAl3, occupies less volume than the elemental titanium and aluminum consumed to produce it. This tends to create voids within a plug.
For instance, a voiding problem has been identified, which is illustrated in FIG. 5 as a void defect 58, as occurring in conventionally fabricated vias having titanium liners. Namely, a breakdown in the dual-layer via lining (54, 55) occurs as shown as a crack through the via lining leading to a cavity or void 58 in the first aluminum interconnection layer 51. The cracked TiN permits free fluorine to attack the exposed aluminum and Tixe2x80x94Al which can create large voids. The presence of such a void space can undermine the performance and reliability of the entire hole connection. For instance, the mechanical strength of the via is reduced due to the presence of the voids. Additionally, if the first aluminum interconnection layer 51 becomes too narrow due to the voiding phenomenon occurring beneath the via, the underlying conducting layer can void out so as to cause a gap in the line resulting in an open circuit condition.
Aluminum plugs also tend to have poor adhesion to a silicon dioxide dielectric layer such that the aluminum plugs can separate or xe2x80x9cde-wetxe2x80x9d from the sidewall of the via hole. This problem can be aggravated by a high aspect ratio (height/width ratio) requirement for the via hole, which makes the hole even harder to fill. A conventional solution to this problem with aluminum plugs has involved depositing a wetting layer of titanium on the walls of the hole before filling the hole with aluminum. However, in conventional aluminum plug processing, titanium aluminide was formed in situ during and concurrent with deposition of the aluminum plug material on the titanium. This also has lead to void problems making it more difficult to achieve a tight via.
Consequently, a need exists in the art for a via having reduced voiding problems and methodology for imparting such increased resistance to void formation and damage.
The present invention resolves the above and other problems that have been experienced in the art. More particularly, the present invention constitutes an advancement in the art by providing a high integrity liner for a via in which a titanium aluminide layer is preformed as a lining within at least part of a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation.
A general method of the present invention for forming such an improved via of a semiconductor device includes forming a dielectric layer over a metallic layer (such as a metal interconnection layer formed over a substrate). A via hole is formed through the dielectric layer to expose a surface portion of the metallic layer at a bottom of the via hole. A preforming of a titanium aluminide layer on the exposed surface portion of the metallic layer is conducted. The titanium aluminide layer can be formed on the bottom only of the via hole or the bottom and sidewalls of the via hole, depending on the embodiment of this invention. Thereafter, a conductive material is deposited in the via hole on the preformed titanium aluminide layer. The semiconductor devices fabricated according to this invention have superior quality and reliability due to the enhanced via formations.
In one particular embodiment, a titanium aluminide layer is preformed at least at the bottom side of a via hole on an exposed surface portion of an underlying aluminum interconnection line before an overlying TiN barrier layer is deposited in the via hole. This procedure significantly prevents cracking of the relatively brittle TiN barrier layer which otherwise would occur during deposition of the refractory metal plug. That is, if the titanium aluminide layer is not preformed according to the present invention in fabrications where a tungsten plug is formed on a TiN layer by reduction of tungsten hexafluoride, then a volume reduction and a shrinkage or contraction of the Tixe2x80x94Al interface will occur during a deposition of the metal plug which will put tension on an overlying TiN layer due to the stress within the layers. Such stress in the layers, which is avoided by the present invention, causes cracks through which fluorine can infiltrate the liner and form voids in the aluminum layer. The present invention prevents such fluorine attack on the underlying aluminum line due to the intervening high integrity (minimally cracked) titanium nitride layer and preformed titanium aluminum layer.
Also, if a TiN barrier liner layer coverage is incomplete or extremely thin in spots, the present invention will prevent fluorine attack on the aluminum lines through those otherwise vulnerable areas on account of the presence of the preformed fluorine-resistant titanium aluminide liner layer. Experiments, described herein, have been conducted which confirm this fluorine barrier capability of titanium aluminide via liners.
The present invention embodies several useful techniques for preforming the titanium aluminide via liners. In one technique, titanium aluminide can be deposited as a discrete layer in place of the conventional titanium layer used in a via hole such that no volume reduction will occur since a titanium aluminide material will already have been formed and line the via hole before TiN deposition and plug metal deposition. A discrete titanium aluminide liner film can be deposited, for example, by sputtering. Another technique for preforming the titanium aluminide liner involves an pre-emptive anneal approach in which a titanium liner film is formed in a via hole and on the exposed surface portion of the underlying aluminum conductor line, and then the deposited titanium film is immediately subjected to heat after its deposition, and prior to TiN deposition, sufficient to form titanium aluminide at the Tixe2x80x94Al interface. As a consequence, the volume reduction associated with titanium aluminide formation occurs in the absence of and without adverse affect upon the TiN layer.
The usefulness of the improved vias of the present invention is not limited to refractory metal plug applications, but also extends to other via plug environments such as aluminum plugs. Additionally, the semiconductor devices made according to this invention are endowed with tight, high-reliability vertical interconnect structures applicable to SRAMs, DRAMs, and many other integrated circuit devices.